When we talk about plasma damage, various issues can be considered, e. g. damage to the silicon crystal during LDD spacer formation or contact etch resulting in junction leakage and/or high contact resistance. In modern low-k interconnect schemas, e. g. plasma ashing by oxygen can increase the k value of the low k material, rendering its costly application useless. But in most cases if we talk about plasma damage we think of degradation of devices like transistors or memory cells by non uniform charging and/or UV radiation during plasma processing. These two effects can cause significant current transport through the gate oxide, changing its electrical characteristic. Therefore gate oxide breakdown and wear-out mechanisms will be reviewed, as a prerequisite, very briefly.
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